Altera Quartus 9.0 SP2 를 기반으로 작성된 소스입니다.


module m_main
(clk,sel,reset,
A,B,A_LED,B_LED,sel_LED,
HEX7,HEX6,HEX5,HEX4,HEX1,HEX0,
status_overflow);
input clk;  //Key1(clk)
input sel;  //iSW17(selector)
input reset; //Key0(reset)
input [7:0] A; //iSW15~08(input switch)
input [7:0] B; //iSW07~00(input switch)
output [7:0] A_LED; //show input status in LEDRx
output [7:0] B_LED; //show input status in LEDRx
output sel_LED;  //show select input status in LEDR17
output [6:0] HEX7; //A input 7segment Display
output [6:0] HEX6; //A input 7segment Display
output [6:0] HEX5; //B input 7segment Display
output [6:0] HEX4; //B input 7segment Display
output [6:0] HEX1; //result 7segment Display
output [6:0] HEX0; //result 7segment Display
output status_overflow; //overflow LEDG0

wire [7:0] input_d_regA; //connected with m_input_D`s output
wire [7:0] input_d_regB; //connected with m_input_D`s output
wire [8:0] result_adder_subtractor; //connected with result_operator
wire overflow_flag;   //connected with overflow result

assign A_LED = A; //show input status
assign B_LED = B;  //show input status
assign sel_LED = sel; //show select input status
assign status_overflow = (overflow_flag==1'b0) ? 1'b0 : 1'b1; //show overflow status

//sub module call
m_input_D U1 (clk, reset, A, input_d_regA),
    U2 (clk, reset, B, input_d_regB); //D_Input
m7SEGMENT U3 (A[7:4], HEX7), //input to 7segment
    U4 (A[3:0], HEX6); //input to 7segment
m7SEGMENT U5 (B[7:4], HEX5), //input to 7segment
    U6 (B[3:0], HEX4); //input to 7segment
m7SEGMENT U7 (result_adder_subtractor[7:4], HEX1), //result to 7segment
    U8 (result_adder_subtractor[3:0], HEX0); //result to 7segment
unsigned_adder_subtractor U9 (input_d_regA, input_d_regB, sel, overflow_flag, result_adder_subtractor);
endmodule


//Data input module
module m_input_D(clk,reset,D,Q);
input clk;
input reset;
input [7:0] D;
output reg [7:0] Q;
always @ (posedge clk or negedge reset) begin
 if(!reset)
  Q <= 8'b0;
 else
  Q <= D;
end
endmodule


//7segment-display module
module m7SEGMENT(D,Q);
input [3:0] D; //4-bit input
output reg [6:0] Q;
always @ (D) begin //stimulate with D
 case (D)
  4'd0: Q = 7'b1000000; //0
  4'd1: Q = 7'b1111001; //1
  4'd2: Q = 7'b0100100; //2
  4'd3: Q = 7'b0110000; //3
  4'd4: Q = 7'b0011001; //4
  4'd5: Q = 7'b0010010; //5
  4'd6: Q = 7'b0000010; //6
  4'd7: Q = 7'b1011000; //7
  4'd8: Q = 7'b0000000; //8
  4'd9: Q = 7'b0011000; //9
  4'd10: Q = 7'b0100000; //A
  4'd11: Q = 7'b0000011; //B
  4'd12: Q = 7'b0100111; //C
  4'd13: Q = 7'b0100001; //D
  4'd14: Q = 7'b0000110; //E
  4'd15: Q = 7'b0001110; //F
  default: Q = 7'b1111111; //off
 endcase
end
endmodule

module unsigned_adder_subtractor
(dataA,dataB,
add_sub,overflow_flag,result);
input [7:0] dataA;
input [7:0] dataB;
input add_sub;   // if this is 1, add; else subtract
output overflow_flag;
output reg [8:0] result;

assign overflow_flag = (result[8]==1'b1) ? 1'b1 : 1'b0;
always @ (dataA or dataB or add_sub) begin
 if (add_sub)
  result <= dataA + dataB;
 else
  result <= dataA - dataB;
end
endmodule

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by Sone 2009.10.14 00:01
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